SK hynix officially announced its next-generation DRAM technology roadmap, including the '4F² (4F Square) VG (Vertical Gate) platform' and 3D DRAM, at the prestigious conference in semiconductor circuit and process technology, 'IEEE VLSI Symposium 2025.'
Chao Seon-yong, head of SK hynix's Future Technology Research Institute (CTO), presented this information during a keynote speech on the theme of 'leading innovation in DRAM technology for a sustainable future' on the 10th.
The IEEE VLSI Symposium is a leading global academic conference where cutting-edge research results on next-generation semiconductors, AI chips, memory, and packaging are presented. It alternates between the United States and Japan every year, and this year it is being held in Kyoto, Japan, for five days starting from the 8th.
Chao noted, 'The current tech platform's application of fine processes has entered a phase where improving performance and capacity is becoming increasingly difficult.' He added, 'To overcome this, we will prepare the 4F²VG platform and 3D DRAM technology based on innovations in structure, materials, and components below 10 nanometers to break through technical limitations.'
The 4F²VG platform is a next-generation memory technology that minimizes the cell area of DRAM and enables the implementation of high-density, high-speed, low-power DRAM through a vertical gate structure.
DRAM stores data at the cell unit level, and the area occupied by one cell is expressed as F² (where F is the minimum line width of the semiconductor). In other words, 4F² means that one cell occupies an area of 2F x 2F, indicating high-density technology to fit more cells within a single chip.
VG refers to a structure in which the gate, performing the switch function of the transistor in DRAM, is positioned vertically and surrounded by a channel.
Currently, 6F² cells are common, but SK hynix explains that by applying wafer bonding technology that positions the circuit portion below the cell area along with 4F² cells, improvements can be expected not only in cell efficiency but also in electrical characteristics.
Chao also presented 3D DRAM as a core pillar of next-generation DRAM technology. While there are observations in the industry that the manufacturing expense of 3D DRAM technology may increase proportionally with the number of layers, SK hynix is determined to overcome this through technological innovation and secure competitiveness.
He also announced plans to advance technology for core materials and overall DRAM components to secure new growth drivers, thus establishing a foundation for continuous evolution of DRAM technology over the next 30 years.
Chao stated, 'Around 2010, many projections indicated that 20 nanometers would be the limit for DRAM technology, but through continuous technological innovation, we have arrived at this point.' He added, 'I will present a medium- to long-term technological innovation vision that will serve as a landmark for young engineers participating in DRAM technology development and, in cooperation with the industry, make the future of DRAM a reality.'
On the last day of the event, the 12th, Park Joo-dong, vice president of SK hynix, who is responsible for the next-generation DRAM task force (TF), will be a presenter. During this session, the latest research results confirming the electrical characteristics of DRAM using VG and wafer bonding technology will also be disclosed.